1. Field of Invention
The invention relates to communication systems, and more particularly to an apparatus for achieving synchronization in digital receivers used in communication systems.
2. Description of the Related Technology
In synchronous digital transmission, information is conveyed by uniformly spaced pulses and the function of any receiver is to isolate these pulses as accurately as possible. However, due to the noisy nature of the transmission channel, the received signal has undergone changes during transmission and a complete estimation of certain reference parameters is necessary prior to data detection. Estimation theory proposes various techniques for estimating these parameters depending on what is known of their characteristics. One such technique is called maximum likelihood (ML). Maximum likelihood estimation assumes the parameters are deterministic or at most slowly varying over the time interval of interest. The term deterministic implies the parameters are unknown but of a constant value and are, therefore not changing over the observation interval. These unknown parameters can cover such factors as the optimum sampling or the phase offset introduced in the channel or induced by the instabilities of the transmitter and receiver oscillators. It is widely recognized that maximum likelihood estimation techniques offer a systematic and conceptually simple guide to the solution of synchronization problems. Maximum likelihood offers two significant advantages: it leads to appropriate circuit configurations and provides near optimum or optimum performance depending on the known channel conditions. See, e.g., J. G. Proakis, xe2x80x9cDigital Communicationsxe2x80x9d, Third Edition, McGraw-Hill Publishers, 1995, pp. 333-336.
Maximum likelihood parameter estimation for communication systems facilitates two forms of processing depending on how the data present on the received signal is exploited to assist in parameter estimation. The first is data-aided (DA) estimation wherein known data within the received data stream is exploited to improve the estimation performance. Alternatively, non-data-aided (NDA) estimation is possible wherein the random data is considered a nuisance parameter, which is removed by averaging the received signal over the statistics of the random data. Applying ML as the criterion to derive the NDA ML timing offset estimator, results in a mathematical expression, which is highly non-linear and totally impractical to implement (i.e., the solution requires calculating the natural logarithm of a hyperbolic cosine function of the received signal samples). However, the ML based timing estimators available in the literature are derived by making suitable approximations for the natural logarithm of the hyperbolic cosine non-linearity for extreme values of signal to noise conditions, which generally yield acceptable performance over a wide range of signal to noise conditions. The variance of the timing estimate depends on the applied approximation. In the present invention, an approximation is applied, which offers an excellent compromise between variance performed and implementation cost for the NDA estimation of a timing offset where a phase offset is present on the received signal.
Generally, if the transmitter does not generate a pilot synchronization signal, the receiver must derive symbol timing from the received signal. The term symbol is used in this context to refer to transmitted signals that are phase and or amplitude modulated with discrete phase and or amplitude relationships; each assigned relationship is a symbol that is subject to detection at the receiver. Both the transmitter and receiver employ separate clocks which drift relative to each other, and any symbol synchronization technique must be able to track such drift. Therefore, choosing the proper sampling instants for reliable data detection is critical, and failure to sample at the correct instants leads to inter-symbol interference (ISI), which can be especially severe in sharply bandlimited signals. The term ISI refers to two or more symbols that are superimposed upon each other. Under these circumstances, phase detection of each symbol becomes extremely difficult. Incorrect sampling implies the receiver is inadvertently sampling where the influence of the previous data symbol is still present. See, e.g., J. G. Proakis, xe2x80x9cDigital Communicationsxe2x80x9d, Third Edition, McGraw-Hill Publishers, 1995, pp. 536-537.
In a digital receiver, the signal following demodulation is first passed through an anti-aliasing filter which is used to limit the bandwidth of the received signal, and is subsequently sampled asynchronously. Asynchronous sampling implies there is no control over the instant at which the sampling of the continuous time signal occurs. FIG. 2 illustrates the concept of oversampling a continuous signal at four samples per symbol. The optimum sampling instants correspond to the maximum eye opening and are located approximately at the peaks of the signal pulses. The term xe2x80x9ceye openingxe2x80x9d refers to the amplitude variations of the signal at the output of the pulse-shaping filter. An xe2x80x9ceyexe2x80x9d is formed by superimposing the output of the pulse shaping filter for each symbol upon the other until the central portion takes on the shape of an xe2x80x9ceyexe2x80x9d as illustrated in FIGS. 1a and 1b for the case of a BPSK (Binary Phase Shift Keying) modulation scheme. Note that under high signal-to-noise conditions, the xe2x80x9ceyexe2x80x9d is open whereas at low signal to noise conditions the xe2x80x9ceyexe2x80x9d is closed.
Among synchronization techniques, a distinction is made between feedforward and feedback systems. A feedback system uses the signal available at the system output to update future parameter estimates. Feedforward systems process the received signal to generate the desired estimate without explicit use of the system output. Whether the design approach is feedforward or feedback, both techniques are related to the maximum likelihood parameter estimation. In an error tracking feedback loop, the timing estimator constantly adjusts the phase of a local clock oscillator to minimize the phase error between the estimated and the optimum sampling instant as illustrated in FIG. 3 The principle is the same for continuous time or sampled input signals Feedforward designs however are applied to sampled input signals. A feedforward timing loop as illustrated in FIG. 4, initially samples the incoming signal, and then using techniques such as interpolation/decimation estimates the ideal sample and removes the redundant samples. Both feedforward and feedback techniques are used in the current technology. However, it should be noted that there are advantages and disadvantages associated with both approaches, which should be understood prior to deciding the appropriate estimator configuration for a particular design.
Problems with feedback techniques include the acquisition time, the high probability of hangup and cycle slips associated with their phase locked loop (PLL) based structures, especially in the presence of fading. Fading occurs when signal components arriving via different propagation paths add destructively. Hangup occurs when the initial phase error of the estimator is close to an unstable equilibrium point, which can result in an extremely long acquisition time (i.e., a long time for the loop to adjust to the correct phase), in fact, the loop may never recover. Hangup is very serious as it can even occur in perfect channel conditions. See, e.g., H. Meyr, M. Moeneclaey and S. A. Fechtel, xe2x80x9cDigital Communication Receivers: Synchronization, Channel Estimation and Signal Processingxe2x80x9d, John Wiley Publishers, 1998, pp.94-97. Cycle slips are very harmful to the reliability of the receiver""s decisions, because a cycle slip corresponds to the repetition or omission of a channel symbol. H. Meyr, M. Moeneclaey and S. A. Fechtel, xe2x80x9cDigital Communication Receivers: Synchronization, Channel Estimation and Signal Processingxe2x80x9d, John Wiley Publishers, 1998, pp.385-399. These issues are solely due to the feedback nature of traditional estimators.
These problems can be circumvented through the use of feedforward estimation. The advantages of feedforward estimation are that acquisition time is solely dependent on loop bandwidth and is not influenced by channel conditions, cycle slipping and hangup do not occur and implementation costs are lower, as feedforward designs are more suited to VLSI (Very Large Scale Integration) implementation. Flexibility in the design of the synchronization unit in a receiver has increased in recent times with the advent of increasingly powerful semiconductor integrated circuits. This has led to the increasing adoption of feedforward estimation techniques and the further development of novel synchronization techniques.
However, feedforward techniques, require a higher oversampling ratio than is prevalent in sampled feedback estimators, see, e.g., F. M. Gardner, xe2x80x9cA BPSK/QPSK Timing Error Detector for Sampled Receiversxe2x80x9d, IEEE Transactions on Communications, COM-44, March 1996, pp399-406; K. H. Mueller and M. Mueller, xe2x80x9cTiming Recovery in Digital Synchronous Data Receiversxe2x80x9d, IEEE Transactions on Communications, COM-24, May 1976, pp516-531, which generally require an oversampling rate of one or two samples per symbol for reliable operation. In feedforward designs the oversampling rate is generally four or more samples per symbol. See, e.g., H. Meyr, M. Moeneclaey and S. A. Fechtel, xe2x80x9cDigital Communication Receivers: Synchronization, Channel Estimation and Signal Processingxe2x80x9d, John Wiley Publishers, 1998, pp.289-295. This is in contrast to classic analog feedback methods, which require a continuous time waveform. See, e.g., J. G. Proakis, xe2x80x9cDigital Communicationsxe2x80x9d, Third Edition, McGraw-Hill Publishers, 1995, pp.358-365. Digital synchronization methods recover timing, by operating only on signal samples taken at a suitable rate. Digital implementation of an estimator has enormous appeal in communications technology and influences the design of all modern receivers because of the flexibility and accuracy of the signal processing algorithms.
There are two distinct stages involved in timing estimation: first the estimation of the timing phase and second the application of this estimate to the sampling process. The choice of ideal sampling instant within the symbol duration is called the timing phase. In a feedback system these are integrated together into one loop, as illustrated in FIG. 3, whereas in feedforward estimation they comprise two very distinct stages in the receiver as illustrated in FIG. 4. The configuration of the feedforward timing estimator loop is very different from that of a feedback loop. FIG. 4 illustrates that the first stage is the asynchronous sampling. In the feedforward arrangement, sampling is typically not directly synchronized to the data symbols and the subsequent processing must choose the optimum sampling instant without the luxury of altering the phase of the sampling clock. This is achieved in the timing phase estimation and timing correction units. An algorithm is applied in the timing phase estimation unit to estimate the timing phase. The final stage of signal synchronization is the timing correction, which is the interpolator/decimator. Interpolation estimates the signal value at the optimum sampling instant using the timing phase from the timing phase estimation unit. See, e.g., H. Meyr, M. Moeneclaey and S. A. Fechtel, xe2x80x9cDigital Communication Receivers: Synchronization, Channel Estimation and Signal Processingxe2x80x9d, John Wiley Publishers, Chapter 9, 1998, pp.505-532. Furthermore, to remove the redundant sampling instants produced by the asynchronous sampling of the received signal, a decimator follows the interpolator. The interpolator is essentially a rate conversion mechanism whereby the signals at the input and output operate at two distinct, yet unrelated sampling rates.
The received noisy signal contains no periodic components because the information symbols have zero mean. However, if the received signal is passed through an appropriate nonlinearity operation, such as the square law nonlinearity, spectral lines are generated in the frequency domain at multiples of the symbol rate as illustrated in FIG. 5b. Exploitation of this and similar nonlinearities in the current technology have been presented in the literature. See, e.g., H. Meyr, M. Moeneclaey and S. A. Fechtel, xe2x80x9cDigital Communication Receivers: Synchronization, Channel Estimation and Signal Processingxe2x80x9d, John Wiley Publishers, 1998, pp.289-295; M. Morelli, A. N. D""Andrea and U. Mengali, xe2x80x9cFeedforward ML-Based Timing Estimation with PSK Signals,xe2x80x9d IEEE Communications Letters, Vol. 1, No. 3, 1997, pp80-82; E. Panayirci and E. Y. Bar-Ness, xe2x80x9cA New Approach for Evaluating the Performance of a Symbol Timing Recovery System Employing a General Type of Nonlinearityxe2x80x9d, IEEE Transactions on Communications, Vol. 44, No. 1, 1996, pp.29-33. The concepts of the frequency and time domain are well known. The class of timing estimators which utilize a nonlinearity of this nature are known as spectral line generating synchronizers. The resulting signal at the output of the nonlinearity is the sum of a periodic signal with period equal to the symbol rate T. This periodic signal can be composed as the sum of sinusoidal components with frequencies 1/T, and multiples thereof. This corresponds to spectral lines at the same frequencies The signal at the output of the nonlinearity enters either a phase locked loop (PLL), or a narrowband bandpass filter. In the case of a narrowband bandpass filter tuned to the channel symbol rate 1/T, the sinusoidal component at frequency 1/T, present at the output of the nonlinearity, is isolated.
Practical timing estimators can never perfectly duplicate the effects of the transmitter clock and the transmission channel. However, a fundamental requirement of any timing estimator is that the average frequency of the transmitter and receiver clock oscillators be identical although an instantaneous phase offset always exists. Timing jitter is a term used to account for the fluctuations between the actual clock phase and the optimum clock phase at the receiver to ensure optimum sampling. The timing offset estimate comprises the ideal timing offset as well as fluctuations due to noise, i.e., timing jitter. The smaller the timing jitter the better the timing estimator. In fact, timing jitter is one of the most important criteria in the selection and analysis of a timing estimator. Timing jitter however, is not a fundamental impairment and can be reduced by improving the estimator design. Therefore, the variance of the timing estimate is critical in the analysis of any estimator. The effect of timing jitter is to increase the amount of ISI present on the decimated output data stream.
There is an alternative to the use of a PLL or a narrowband bandpass filter to isolate the spectral component at the symbol rate. This involves evaluating the Fourier component of the signal samples at the output of the nonlinearity for the spectral line occurring at the symbol rate. The phase of the spectral line at the symbol rate is related to the normalized timing offset. The accuracy of this technique depends on the observation interval over which the Fourier component is evaluated. As the observation interval increases, the jitter reduces. However, rather than increasing the observation interval, the jitter performance can also be improved by using alternative nonlinearities. See e.g., M. Morelli, A. N. D""Andrea and U. Mengali, xe2x80x9cFeedforward ML-Based Timing Estimation with PSK Signals,xe2x80x9d IEEE Communications Letters, Vol. 1, No. 3, 1997, pp80-82; E. Panayirci and E. Y. Bar-Ness, xe2x80x9cA New Approach for Evaluating the Performance of a Symbol Timing Recovery System Employing a General Type of Nonlinearityxe2x80x9d, IEEE Transactions on Communications, Vol. 44, No.1, 1996, pp.29-33.
ML theory states that joint estimation of all the unknown parameters in a system is the optimal approach for detecting data in white noise. However, joint estimation is not always used, due to issues related to the interdependence of the estimation of all parameters simultaneously. In practice, independent estimation of the parameters is preferred. However, care must be taken in the choice of parameter estimators for a receiver. If the timing estimator is among the first units in the baseband receiver system, then its performance should be independent of the presence of a phase offset on the sampled received signal which is deterministic or at most slowly varying over the observation interval. In general, a phase offset is considered to be slowly varying if its phase changes by less than 10xe2x88x923 over the observation interval. To date, in the literature few timing estimators can meet this challenge.
Consequently, what is desired is to provide a timing estimation method which can give comparable performance in the presence of a slowly varying or static phase offset as algorithms which require that the phase offset be removed beforehand. Timing estimation based on the information obtained from the sampled pulse shaping output in a digital receiver using four samples per symbol is also needed. A mechanism for timing estimation when knowledge of the data stream or subsection of the data stream (i.e., a training sequence) can not be used to assist in the estimation is also needed. An alternative method of timing estimation, which provides improved jitter performance over the square law nonlinearity spectral line estimator established in the literature, see, e.g., H. Meyr, M. Moeneclaey and S. A. Fechtel, xe2x80x9cDigital Communication Receivers: Synchronization, Channel Estimation and Signal Processingxe2x80x9d, John Wiley Publishers, 1998, pp.289-295, without compromising the relative ease of implementation associated with a square law non-linearity is also needed.
The present invention provides a system and method of timing estimation for use in a digital receiver within a communication system. A timing estimation block is provided within a digital receiver, where the input signal is processed at four or more samples per symbol and the estimation block is feedforward.
The algorithm calculates the timing offset by evaluating the spectral component at the symbol clock frequency. The spectral component is generated using a nonlinearity operation. The maximum likelihood derivation of a NDA timing estimator indicates an alternative approximation for the logarithm of the hyperbolic cosine function present in the maximum likelihood equation. The estimated timing offset is then fed to a timing correction unit, which calculates the data samples corresponding to the sampling clock phase and removes the redundant samples. The ideal sampled signal is then forwarded to additional synchronization and functional units for further processing.
This method is provided for a variety of digital receivers employing Code Division Multiple Access (CDMA), in which a transmitted signal is spread over a band of frequencies much wider than the minimum bandwidth required to transmit the signal; Time Division Multiple Access (TDMA), where the users share the radio spectrum in the time domain; Frequency Division Multiple Access (FDMA) where a user is allocated at least one unique frequency for communication without interference with users in the same frequency spectrum and or any combination of the principles of the above or other technologies.
In one aspect of the present invention, a digital receiver system comprises an anti-aliasing filter, a sampling unit, a filtering block, a timing estimation block, a timing correction block and additional synchronization and functional units block. The filtering block comprises a pulse-shaping filter. The timing estimation subsystem comprises a magnitude squaring law nonlinearity, a square law non-linearity, a scaler gain block, a subtraction operation, a complex multiplication operation, a read only memory (ROM) to store the exponential coefficients, an accumulator and a phase calculator lookup table. The filtering block receives the input signal from an intermediate frequency (IF) block which has been demodulated to baseband. In one embodiment, this signal is fed to an anti-aliasing filter to limit the bandwidth of the received signal and then sampled at the analog-to-digital converter (ADC) with a fixed clock (Sampling Clock =46.7 MHz). Note that the signals received by the filtering block within the digital receiver might not be sampled, and that the sampling may take place only after the filtering block. The signals output from the filtering block are then fed to the timing estimation subsystem for further processing. The resulting timing estimate is then fed to the timing correction unit to correctly estimate the received data stream. The output from the timing correction unit is subsequently fed to additional functional blocks for further processing.
Another aspect of the invention includes a timing estimation circuit, comprising an instantaneous likelihood function circuit capable of approximating the natural logarithm of the hyperbolic cosine of a sampled filtered signal; a multiplier receivably connected to the approximation circuit and receivably connected to a source for exponential coefficients and outputting sampled Fourier components; a summer receivable connected to the multiplier for summing each sampled Fourier component; and a phase calculator receivable connected to the summer to provide a timing offset signal.
Yet another aspect of the invention includes a timing synchronization circuit for a baseband subsystem of a digital receiver, comprising a delay circuit receiving a sampled filtered signal; a timing estimation circuit receiving the sampled filtered signal and including a natural logarithm of the hyperbolic cosine approximation circuit; and a timing correction circuit receivably connected to the delay circuit and the timing estimation circuit.
Still another aspect of the invention includes an instantaneous likelihood function circuit, comprising means for magnitude squaring a sampled filtered signal; means, receivably connected to the magnitude squaring means, for scaling the magnitude squared signal; means, receivably connected to the magnitude squaring means, for squaring the magnitude squared signal; and a subtracter to subtract the signals received from the squaring means and the scaling means.